Prof. Manoli is pleased to invite you to the guest lecture of Mr. Pavel Livshits, Freescale Semiconductor; Bar Ilan University, Israel

Distributed Properties of On-Die Interconnects in Nano Scale VLSI Devices



The VLSI design has been making huge strides forward for the last decade. At the same time a continuous shrinking of VLSI devices, necessity to transfer data over relatively long distances across a die, reduction of voltage noise margins and steadily expansion of digital circuits’ bandwidth inevitably resulted in a toughening of signal integrity requirements and made challenges stood before ICs designers more intractable. In our work we study distributed properties of on-die interconnection lines for power supply networks and data transfer. The local voltage fluctuations in the supply and ground grids triggered by on-die logic cell switching have been experimentally studied employing typical VLSI chips. The results show that these fluctuations have a resonant-like form i.e., the on-die power grid should be described as an RLC circuit. The studies reveal that the active element (i.e., CMOS logic cell) affects the frequency properties of power supply and ground grids during its switching (as opposed to before or after switching). It is found that the frequency properties of the both grids are inter-related via the interconnecting active elements. The recorded voltage waveforms inside a working chip can, under certain conditions, oscillate locally with amplitudes that reach more than 10% of the supply bias. This considerably augments device degradation caused by wearout mechanisms, such as Negative Bias Temperature Instabilities (NBTI), Hot Carrier Injection (HCI) and Time Dependent Dielectric Breakdown (TDDB). The on-die transmission lines were experimentally studied as an alternative to carry out on-die global signaling. The obtained signal waveforms from a test chip, performed on a 45 nm CMOS technology process, reveal that the on-die impedance matching may play an essential role in on-die circuit performance and reliability. It has been shown that the device aging of receiver transistors due to wearout mechanisms, such as TDDB and HCI may be considerably accelerated as a result of even a small impedance mismatch between driver output impedance and characteristic impedance of driven line. In addition, it has been demonstrated that impedance mismatch leads to power waste and the mismatchinduced functionality problems may lead to system failure.


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